1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device for performing an operation for dividing blocks and a method for controlling the same.
2. Description of the Prior Art
FIG. 1 is a diagram showing a part of a pair of bit lines in a conventional dynamic semiconductor memory device, which is described in an article entitled "A 288K CMOS Pseudostatic RAM", IEEE Journal of Solid-State Circuits, Vol SC-19, No. 5, Oct. 1984, pp. 619-623.
In FIG. 1, a plurality of word lines WL are arranged to intersect with a bit line pair BL and BL, a memory cell MC being provided at an intersection of each of the bit lines BL and BL and each of the word lines WL. In FIG. 1, only a single memory cell MC connected to the bit line BL and a single memory cell MC connected to the bit line BL are illustrated and the other memory cells are omitted. Each of the memory cells MC comprises a transferring transistor Qs and a storing capacitor C. The transistor Qs is connected between the bit line BL or BL and the storing capacitor C and has its gate connected to the word line WL.
In addition, an N type sense amplifier NSA and a P type sense amplifier PSA are connected to the bit line pair BL and BL. The N type sense amplifier NSA comprises N channel MOS transistors Q1 and Q2. The transistor Q1 is connected between the bit line BL and a node N1 and has its gate connected to the bit line BL. The transistor Q2 is connected between the bit line BL and the node N1 and has its gate connected to the bit line BL. The node N1 is coupled to a ground potential through an N channel MOS transistor Q3. The transistor Q3 has its gate receiving a sense amplifier activating signal .phi.S.sub.N. The P type sense amplifier PSA comprises P channel MOS transistors Q4 and Q5. The transistor Q4 is connected between the bit line BL and a node N2 and has its gate connected to the bit line BL. The transistor Q5 is connected between the bit line BL and the node N2 and has its gate connected to the bit line BL. The node N2 is coupled to a power-supply potential V.sub.CC through a P channel MOS transistor Q6. The transistor Q6 has its gate receiving a sense amplifier activating signal .phi.S.sub.P. In addition, an equalizing N channel MOS transistor Q7 is connected between the bit lines BL and BL and has its gate receiving an equalize signal BLEQ.
Referring to a waveform diagram of FIG. 2, description is made on operation of the circuit shown in FIG. 1.
When a row address strobe signal RAS is at an "H" level, i.e., in an off time period, the sense amplifier activating signal .phi.S.sub.N attains the "H" level and the sense amplifier activating signal .phi.S.sub.P attains an "L" level, so that the sense amplifiers NSA and PSA are rendered active. Consequently, a potential on one of the bit lines BL and BL is held at the "H" level and a potential on the other bit line is held at the "L" level.
Then, when the row address strobe signal RAS is at the "L" level, i.e., in an active period, the sense amplifier activating signal .phi.S.sub.N is forced to be the "L" level and the sense amplifier activating signal .phi.S.sub.P is forced to be the "H" level, so that the sense amplifiers NSA and PSA are rendered inactive. Thereafter, the equalize signal BLEQ is once forced to be the "H" level, so that the bit line pair BL and BL is short-circuited. Consequently, both the potentials on the bit lines BL and BL attain an intermediate potential (precharge potential) level between the "H" level and the "L" level. The equalize signal BLEQ is returned to the "L" level and then, a word line driving signal .phi.W.sub.L rises to the "H" level. Consequently, information stored in the memory cell MC connected to the selected word line WL is read out to a corresponding bit line BL or BL, so that a potential on the bit line BL or BL slightly rises or lowers in response to the information stored in the memory cell MC. On this occasion, a potential on the bit line BL or BL to which the selected memory cell MC is not connected remains at the above described precharge potential level. Thereafter, when the sense amplifier activating signal .phi.S.sub.N is forced to be the "H" level and the sense amplifier activating signal .phi.S.sub.P is forced to be the "L" level so that the sense amplifiers NSA and PSA are rendered active, the potential difference between the bit lines BL and BL is amplified. As a result, a higher potential of the potentials on the bit lines BL and BL is fixed at the "H" level and a lower potential is fixed at the "L" level. In the above described manner, refresh and read operations of the memory cell MC are performed. Thereafter, when the row address strobe signal RAS rises to the "H" level, the active period is completed, so that the word line driving signal .phi.WL falls to the "L" level. Consequently, a transistor Qs in the memory cell MC connected to the selected word line WL is turned off. However, the sense amplifiers NSA and PSA remain in an active state until the next active period is started. When the row address strobe signal RAS attains the "L" level so that the active period is started, the above described operations are performed again.
Meanwhile, in many cases, the recent dynamic semiconductor memory device has been adapted such that an operation for dividing a memory cell array is performed in order to decrease operating current. More specifically, the memory cell array is divided into a plurality of blocks, so that bit lines are charged or discharged only in a block selected by a part of inputted address signals.
When a memory cell array having structure shown in FIG. 1 is applied to a block partitioned semiconductor memory device, as shown in FIG. 2B, the row address strobe signal RAS falls to the "L" level and then, an address signal AD is decoded, so that a block is selected by the address signal AD. The equalize signal BLEQ in only the selected block rises to the "H" level, so that the potential on the bit line pair BL and BL is equalized. Thus, the equalize signal BLEQ cannot be forced to be the "H" level until the address signal AD has decoded after the row address strobe signal RAS fell to the "L" level, so that access is delayed. If the operation for dividing the memory cell array is not performed, a block need not be selected. Consequently, the equalize signal BLEQ can be raised to the "H" level immediately after the row address strobe signal RAS attains the "L" level, so that access is not delayed.
FIG. 3 is a diagram showing a part of one pair of bit lines in another conventional dynamic semiconductor memory device, which is described in, for example, an article entitled "A Fast 256K.times.4 CMOS DRAM with a Distributed Sense and Unique Restore Circuit", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 861-867.
A circuit shown in FIG. 3 is the same as the circuit shown in FIG. 1 except that bit lines BL and BL are connected to a precharge potential generating circuit PR through precharging N channel MOS transistors Q8 and Q9, respectively. The transistors Q8 and Q9 have their gates receiving an equalize signal BLEQ which is also applied to an equalizing transistor Q7. The precharge potential generating circuit PR generates a precharge potential V.sub.BL. The precharge potential V.sub.BL is an intermediate potential 1/2.multidot.V.sub.CC between a power-supply potential V.sub.CC and a ground potential.
Referring now to a waveform diagram of FIG. 4, description is made on operation of the circuit shown in FIG. 3.
In the circuit, immediately after the refresh and read operations of a memory cell MC are completed so that a row address strobe signal RAS rises to the "H" level and then, a word line driving signal .phi.WL attains the "L" level, a sense amplifier activating signal .phi.S.sub.N attains the "L" level and a sense amplifier activating signal .phi.S.sub.P attains the "H" level, so that sense amplifiers NSA and PSA are rendered inactive. The equalize signal BLEQ immediately attains the "H" level, so that the bit line pair BL and BL is short-circuited. Thus, in a block partitioned semiconductor memory device using this circuit, when decoding of the address signal is completed, the equalize signal BLEQ in a selected block can be immediately forced to be the "L" level and the word line driving signal .phi.WL can be raised to the "H" level, so that access is never delayed.
In the above described operation, while the row address strobe signal RAS is at the "H" level, a potential on the bit line pair BL and BL is equalized to be a precharge potential at an intermediate potential level between the "H" level and the "L" level. However, if the time period during which the row address strobe signal RAS is at the "H" level is long, the potential on the bit line pair BL and BL deviates from the above describe precharge potential by the effect of a leak current or the like. In order to hold constant the potential on the bit line pair BL and BL, the precharge potential generating circuit PR is required.
In FIG. 3, when the equalize signal BLEQ attains the "H" level, the transistor Q7 is turned on so that the potential on the bit line pair BL and BL is equalized and at the same time, the transistors Q8 and Q9 are turned on, so that the bit line pair BL and BL is connected to the precharge potential generating circuit PR. Consequently, the precharge potential V.sub.BL is supplied to the bit line pair BL and BL, so that the potential on the bit line pair BL and BL is held constant.
FIG. 5 is a diagram showing an example of a precharge potential generating circuit, which is described in the same document as that describing the circuit shown in FIG. 3.
The precharge potential generating circuit PR comprises an enhancement type N channel MOS transistors Q11, Q12 and Q13, enhancement type P channel MOS transistors Q14, Q15 and Q16, and resistors R1 to R4 having the same resistance value. The resistor R1, the transistor Q11, the transistor Q12 and the resistor R2 are connected in series between a power-supply potential supplying portion V1 and a ground potential supplying portion V2. The transistor Q11 has its gate connected to a node N3 of the resistor R1 and the transistor Q11. The transistor Q12 has its gate connected to a node N4 of the transistors Q11 and Q12. In addition, the resistor R3, the transistor Q14, the transistor Q15 and the resistor R4 are connected in series between the power-supply potential supplying portion V1 and the ground potential supplying portion V2. The transistor Q14 has its gate connected to a node N5 of the transistors Q14 and Q15. The transistor Q15 has its gate connected to a node N6 of the transistor Q15 and the resistor R4. In addition, an output portion comprising the transistors Q13 and Q16 is connected between the power-supply potential supplying portion V1 and the ground potential supplying portion V2. The transistor Q13 is connected between the power-supply potential supplying portion V1 and an output portion 0 and has its gate connected to the node N3. The transistor Q16 is connected between the ground potential supplying portion V2 and the output portion 0 and has its gate connected to the node N6. The power-supply potential supplying portion V1 is coupled to a power-supply potential V.sub.CC and the ground potential supplying portion V2 is coupled to a ground potential.
Assuming that threshold voltages of the N channel MOS transistors Q11 to Q13 are represented by V.sub.THN (&gt;0) and threshold voltages of the P channel MOS transistors Q14 to Q16 are represented by V.sub.THP (&lt;0), a potential of the node N3 is V.sub.CC /2+V.sub.THN and a potential of the node N6 is V.sub.CC /2 +V.sub.THP. Consequently, when a potential of the output portion O is V.sub.CC /2 or less, the transistor Q13 is rendered conductive and the transistor Q16 is rendered non-conductive, so that the potential of the output portion O is raised. On the other hand, when the potential of the output portion O is V.sub.CC /2 or more, the transistor Q13 is rendered non-conductive and the transistor Q16 is rendered conductive, so that the potential of the output portion O is lowered.
Meanwhile, in the precharge potential generating circuit PR, current flows through a path comprising the power-supply potential supplying portion V1, the resistor R1, the transistor Q11, the transistor Q12, the resistor R2 and the ground potential supplying portion V2 and a path comprising the power-supply potential supplying portion V1, the resistor R3, the transistor Q14, the transistor Q15, the resistor R4 and the ground potential supplying portion V2. In addition, subthreshold current constantly flows through the transistors Q13 and Q16. Thus, current at the standby time is increased.
Recently, since a portable personal computer has been widely used, storage is held by a buttery also in a dynamic semiconductor memory device. Thus, current required to hold storage must be decreased. In the dynamic semiconductor memory device, the semiconductor memory device generally enters a standby state and a refresh operation is performed the minimum of times as required, so that storage is held. Thus, in order to decrease the current required to hold storage, either or both of standby current and refresh current must be decreased. However, constant current flowing through the above described precharge potential generating circuit causes both the standby current and the refresh current to be increased.
In the conventional block partitioned semiconductor memory device shown in FIGS. 1 and 2, the bit line pair of BL and BL must be equalized after address decoding is completed as described above, so that access is delayed. In addition, in the conventional block partitioned semiconductor memory device shown in FIGS. 3 and 4, the constant current flowing through the precharge potential generating circuit causes the current at the time of the operation and the current required to hold storage to be increased.